Field
This disclosure relates generally to semiconductor devices, and more specifically, to placing vias to minimize time dependent dielectric breakdown.
Related Art
Backend Time Dependent Dielectric Breakdown (TDDB), also referred to as electrical shorts, can develop over time between a via (Vx) and an adjacent upper and lower metal layers (Mx+1 and Mx). TDDB can become a major reliability problem in advanced technology nodes where devices, and the spacing between them, are ever decreasing in size.
Referring to FIG. 13, a side cross-sectional view of an example of a via 1302 between a first metal line 1304 and a second metal line 1306 that are part of a first connection net (net 1) is shown. A third metal line 1310 is shown in the same metal layer as metal line 1306, however metal line 1310 is part of a second connection net (net 2). FIG. 14 shows a partial top view of the via 1302 and metal lines 1304, 1306, 1310 of FIG. 13. TDDB problems arise because the exterior sidewall 1308 of via 1302 has a tapered profile where the top portion of via 1302 at metal line 13 1304 has a larger cross-sectional diameter than the bottom portion of via 1302 at metal line 1306. The dielectric material between the top edge of via 1302 and neighboring metal line 1310 (denoted as dtop) may break down over time, causing a short between the first and second connection nets. To avoid reliability issues due to TDDB, common practices are to set a maximum (relatively small) number of vias that can be placed adjacent metal lines, or use a larger spacing rule for routing metal layers which requires more space. Accordingly, further improvements to minimize space required while still providing the desired number and location of via contacts in a given area, are sought.